Memory addressing device

Details Memory addressing device Memory addressing device

1984-11-13

1988-02-23

Harkcom, Gary V.

Boots, shoes, and leggings

365236, 377 46, 377 54, G06F 700, G11C 800

Patent

active

047274816

ABSTRACT:
An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever the first word of the address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.

REFERENCES:
patent: 3749845 (1983-07-01), Fraser
patent: 3992699 (1976-11-01), Krumbach
patent: 4016545 (1977-04-01), Lipovski
patent: 4047247 (1977-09-01), Stanley et al.
patent: 4115867 (1978-09-01), Vladimirov et al.
patent: 4202035 (1980-05-01), Lane
patent: 4393482 (1983-07-01), Yamada
patent: 4503525 (1985-03-01), Malik et al.

Affiliated with

Also associated with

Rating

Memory addressing device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory addressing device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory addressing device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-606084