Data processing apparatus with improved mechanism for executing

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395412, 395800, G06F 930

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active

056447469

ABSTRACT:
A data processing apparatus, having a visible register map for associating physical registers with logical registers. Instructions involving register-to-register transfers are executed by altering the association between the physical registers and the logical registers, without actually transferring data between the registers, so as to avoid logically redundant operations and to take such instructions out of the critical path of execution.

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Upper and Lower Bounds for One-Write Multivalued Regular Register by Chaudhuri et al, IEEE 1991 Publication (pp. 134-141).
Implementation of the PIPE processor, by Matthew K Farrens et al, Jan. 1991 Publication (pp.-65-70).
Bullions, "Resolving Store-Load Links in an Instruction Unit", IBM Technical Disclosure Bulletin, vol. 14, No. 3, Aug. 1971, pp. 868-869.
"High-Performance Register-to-Register Transfer Instructions," IBM Techncial Disclosure Bulletin, vol. 32, No. 11, Apr. 1990, pp. 368-369.

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