Processor with single clock decode architecture employing single

Details Processor with single clock decode architecture employing single Processor with single clock decode architecture employing single

1993-10-18

1997-07-01

Harrell, Robert B.

G06F 922

Patent

active

056447418

ABSTRACT:
A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.

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