Patent
1995-06-07
1997-07-01
Barry, Lance Leonard
395651, 395652, 395653, G06F 1202
Patent
active
056447329
ABSTRACT:
A method and apparatus for providing address designations for a three dimensional computer system arranged in a plurality of planar layers is disclosed. Each layer comprises an incrementer for generating a layer identification value. A first layer has a starting value, representing the first layer identification value, and an incremental value which is added to the starting value to generate a second layer identification value. In this way, each incrementer on each layer is serially coupled to a next higher layer. A control processor accesses file information on each layer through use of the layer identification value. The register file identifies the layer as a memory module, processor module or input/output interface module. From the information contained within the register file, the control processor assigns an address to each of the layers. In addition, the control processor writes initialization parameters to the register file. The address and parameter data is then transferred to the module circuitry on the corresponding layer.
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Barry Lance Leonard
Sun Microsystems Inc.
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