Program counter mechanism having selector for selecting up-to-da

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395375, 364DIG1, 3642472, 3642476, 3642551, 3642558, G06F 932

Patent

active

054598478

ABSTRACT:
A program counter for a prefetch mechanism in a stored program arithmetic unit for generating an instruction address of an immediately succeeding instruction by using a portion of or the entire prefetch address and a current instruction address, includes a prefetch address generator and an instruction address generator. The prefetch address generator includes a first n-bit register storing a current prefetch address, an n-bit adder for obtaining a next prefetch address, and a first n-bit selector. The instruction address generator includes a second n-bit register storing a current instruction address, an m-bit adder, an (n-m)-bit selector and a second n-bit selector.

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patent: 4764861 (1988-08-01), Shibuya
patent: 4860197 (1989-08-01), Langendorf et al.
patent: 4926323 (1990-05-01), Baror et al.
patent: 4984154 (1991-01-01), Hanatani et al.
patent: 5168557 (1992-12-01), Shibuya
patent: 5197141 (1993-03-01), Ito

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