Process for forming a self-aligned low resistance path in semico

Details Process for forming a self-aligned low resistance path in semico Process for forming a self-aligned low resistance path in semico

1986-05-23

1987-06-02

Smith, John D.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 156662, 427 93, H01L 21425

Patent

active

046691782

ABSTRACT:
A method of forming a low resistance path, e.g., to serve as a guard ring, in a silicon semiconductor device is disclosed.
An opening is defined in an upper protective layer and an underlying lower protective layer. Normally these layers are silicon nitride and silicon dioxide, respectively. The lower protective layer is isotropically wet etched so that the upper protective layer overhangs the lower protective layer and protects a part of the silicon wafer surface.
A first impurity is implanted in the exposed silicon wafer surface except in the annular area protected by the upper protective layer overhang.
A silicon dioxide layer is grown on the entire exposed surface of the silicon wafer which is inherently thicker over the area where the impurity has been implanted and inherently thinner over the annular area where the impurity has not been implanted. The upper protective layer is then preferably removed.
A second impurity is implanted through the annular thinner silicon dioxide layer, which optionally may be etched away, to create, e.g., a guard ring in the silicon wafer around the perimeter of the thicker silicon dioxide layer which has protected the silicon wafer from the implant.

REFERENCES:
patent: 4261095 (1981-04-01), Dreves
patent: 4481041 (1984-11-01), Muller
patent: 4558508 (1985-12-01), Kinney
patent: 4597827 (1986-07-01), Nishitani

Affiliated with

Also associated with

Rating

Process for forming a self-aligned low resistance path in semico does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming a self-aligned low resistance path in semico, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming a self-aligned low resistance path in semico will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-604818