Two phase CMOS shift register bit for optimum power dissipation

Details Two phase CMOS shift register bit for optimum power dissipation Two phase CMOS shift register bit for optimum power dissipation

1990-05-07

1991-01-15

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

307279, 377 72, H03K 2344, H03K 3286, G11C 11412

Patent

active

049859056

ABSTRACT:
Apparatus for formation of a two-phase shift register bit that preserves noise margins, allows use of reduced standby power, requires only two clock phase signals to drive the system, and requires relatively few transistors for implementation. In one embodiment, the apparatus uses two modules that are substantially identical, each module using four transistors and requiring only a single clock phase signal for operation.

REFERENCES:
patent: T913008 (1973-08-01), Beausoleil
patent: 3586875 (1971-06-01), Nicklas
patent: 3641360 (1972-02-01), Yao
patent: 3665210 (1972-05-01), Ho et al.
patent: 3812384 (1974-05-01), Skorup
patent: 4322635 (1982-03-01), Redwine
patent: 4446567 (1984-05-01), Iida et al.
patent: 4484087 (1984-11-01), Mazin et al.
patent: 4703200 (1987-10-01), Zangara
patent: 4705965 (1987-11-01), Stuyt
IBM Tech. Disclosure Bul. vol. 12, No. 12 pp. 2144, 2145-May, 1970 "Complementary FET Dynamic Shift Register Using Single Phase Line" by Gaensslen et al.

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