Scan path circuit for testing multi-phase clocks from sequential

Details Scan path circuit for testing multi-phase clocks from sequential Scan path circuit for testing multi-phase clocks from sequential

1993-05-20

1995-10-17

Voeltz, Emanuel T.

Excavating

371 251, 3241581, G01R 3128

Patent

active

054597366

ABSTRACT:
A scan path circuit for testing multi-phase clocks of sequential circuits is capable of preventing a clock skewing and includes a plurality of scan circuits coupled to respective clock testing circuits each including a latch circuit receiving a clock signal and a clock mode signal to output a latch output signal, and a control gate which outputs a control signal. The scan circuits each includes two latch circuits and a control gate which receives a test clock signal. The scan circuits operate as flip-flops during a non-testing period. When a scan mode signal is "0" and a clock signal is "1" an output of the latch circuit of the testing circuit becomes "1" and an output of the control gate thereof becomes a value of a first test clock signal. This value is used as a clock of the scan circuit, and a data input signal is taken into the respective scan circuit. When the clock signal is "0", the output of the latch circuit of the clock testing circuit becomes "0" and the output of the control gate thereof becomes "0". Thus, no input data is taken into the scan circuit, and a value of a scan input is held.

REFERENCES:
patent: 4534028 (1985-08-01), Trischler
patent: 4669061 (1987-05-01), Bhavsar
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4942577 (1990-07-01), Osaki
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5130646 (1992-07-01), Kojima
patent: 5130647 (1992-07-01), Sakashita et al.

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