Real-time DC offset control and associated method

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G06J 100

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active

054596793

ABSTRACT:
An apparatus and method for removing direct current (DC) offset from a received analog signal having DC offset introduced during analog signal processing. The preferred circuit has a DC offset control loop that is enabled and operates in real-time during the reading of a sinusoidal preamble pattern. The control loop rapidly cancels DC offset by subtracting a learned correction value from the incoming analog signal being processed. Before end of preamble playback the loop is disabled and the learned correction value held during data read times. The DC offset control loop is not dependent upon correct sampling phase decisions in order to properly determine the DC offset correction value, and it is orthogonal with respect to the gain and timing control loops in a sampled data system thereby minimizing cross-talk or other interference between the several control loops.

REFERENCES:
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patent: 5258933 (1993-11-01), Johnson et al.
patent: 5341249 (1994-08-01), Abbott et al.
patent: 5341387 (1994-08-01), Nguyen
National Semiconductor Corp., Mass Storage Handbook, 1989 Ed., pp. iii, iv, 9-28 through 9-33.
Schmerbeck, Richetta, Smith, "A 27 MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection", Proc. IEEE Int'l Solid State Circuits Conf., 1991, Paper TPM 8.3.

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