Method of manufacturing a non-volatile memory

Details Method of manufacturing a non-volatile memory Method of manufacturing a non-volatile memory

1985-10-29

1988-02-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 52, 437193, 437 235, H01L 21265, H01L 21283

Patent

active

047270438

ABSTRACT:
An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.

REFERENCES:
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patent: 4302766 (1981-11-01), Gutterman et al.
patent: 4361847 (1982-11-01), Harari
Carter, G. et al., Ion Implanatation of Semiconductors, John Wiley & Sons, New York, 1976, pp. 193-194.
Scheibe et al., "Technology of . . . SIMOS", in IEEE Transactions on Electron Devices, vol. ed. 24, No. 5, May 1977, pp. 600-606.
Rossler, B., "Electrically Erasable . . . SIMOS One-Transistor Cell", in IEEE Trans. on Electron Devices, 24(5), May '77, pp. 606-610.
Beyer et al, "Reduction of Oxidation-Induced Defects Using Reactive Ion Etching", IBM Tech. Discl. Bulletin, vol. 22, #2, 7/79.

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