Test pattern generator

Details Test pattern generator Test pattern generator

1986-09-30

1988-07-19

Fleming, Michael R.

Excavating

371 25, G06F 1122

Patent

active

047590211

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to semiconductor testing devices of LSI or the like, and more particularly to a test pattern generator wherein a large number of test patterns to be used in testing of a micro processor or the like are favorably generated at high speed.
In general, in testing of a logic LSI of a micro processor or the like, test patterns are previously stored in a memory of the testing device and then read at high speed, and thereby the test patterns are generated.
Since micro processors with high speed and high function have been developed in recent years, a large number of test patterns must be generated at very high speed in the testing thereof. In order to read the test patterns at high speed using a memory of low speed and large capacity, an interleave operation is known as the most effective means. As a test pattern generator using this means, for example, a device disclosed in Japanese patent application laid-open No. 128646/1979 is known. In testing of a logic LSI or the like, not only the test patterns are read in sequence, but also a function of reading one test pattern repeatedly and a function of branching the reading sequence are required. In the above-mentioned example of the prior art, in order to obtain these functions, a low-speed large-capacity memory is operated in an interleave manner and the output is stored in a high-speed small-capacity memory, and the repeated reading or the branch reading is performed. In this arrangement, however, since branching beyond the capacity of the high-speed memory is impossible, the test patterns cannot be read in an entirely arbitrary sequence.


SUMMARY OF THE INVENTION

An object of the invention is to provide a test pattern generator wherein test patterns of a large number can be read and generated at high speed in an arbitrary sequence.
The invention is characterized in that a high-speed small-capacity memory is provided in addition to a low-speed large-capacity memory operating in an interleave manner, test patterns after branch are previously stored in the memories, when the test patterns are to be read in sequence they are read from the low-speed large-capacity memory, and when a branch is produced in the reading sequence the reading is changed to the high-speed small-capacity memory and the test patterns are read from the high-speed small-capacity memory until the reading from the low-speed large-capacity memory agains becomes possible.


BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic block diagram of a test pattern generator as an embodiment of the invention;
FIG. 2 is a diagram illustrating information stored in memories shown in FIG. 1;
FIG. 3 is a diagram illustrating operation of the generator shown in FIG. 1;
FIG. 4 is a detailed diagram at low-speed memory side shown in FIG. 1;
FIG. 5 is a detailed diagram illustrating operation of circuits shown in FIG. 4;
FIG. 6 is a detailed diagram at high-speed memory side shown in FIG. 1;
FIG. 7 is a detailed diagram illustrating operation of circuits shown in FIG. 6;
FIG. 8 is a digram illustrating calculation of WAIT count;
FIG. 9 is a schematic block diagram illustrating another embodiment of the invention; and
FIG. 10 is a diagram illustrating operation of the generator shown in FIG. 9.


DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the invention will now be described with reference to the accompanying drawings.
FIG. 1 is an overall block diagram of a test pattern generator. The test pattern generator in the embodiment comprises four low-speed large-capacity memories 11, 12, 13, 14 and a high-speed small-capacity memory 50, an interleave controller 20 and a selector 61 for controlling interleave operation of the low-speed large-capacity memories 11, 12, 13, 14 so as to read data from the low-speed large-capacity memories 11, 12, 13, 14 and the high-speed small-capacity memory 50, and a high-speed memory access controller 40 which performs control to read data from the high-speed small-capacity memory 50 when a branch occurs in the rea

REFERENCES:
patent: 4369511 (1983-01-01), Kimura
patent: 4389727 (1983-06-01), Nigorikawa
patent: 4547861 (1985-10-01), Lauiron
patent: 4639919 (1987-01-01), Chang
patent: 4670879 (1987-06-01), Okino

Affiliated with

Also associated with

Rating

Test pattern generator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test pattern generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test pattern generator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-601791