Patent
1977-05-31
1980-11-18
James, Andrew J.
357 23, 357 59, 357 68, H01L 2348, H01L 2946, H01L 2954
Patent
active
042348897
ABSTRACT:
A double-level polycrystalline silicon structure for an N-channel MOS integrated circuit is disclosed including a metal interconnect level. Contact between the metal interconnect level and N+ diffused moat areas is made through discrete second-level polysilicon areas which reduce the step from metal level to moat level, thus increasing yields. Also, connections from the metal level to the first level polysilicon are made using a discrete area of second level polysilicon to minimize the step.
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IBM Technical Disclosure Bulletin; by Smith, Vertical One-Device Memory Cell; vol. 15, No. 12, May, 1973, p. 3585.
Lien Jih-Chang
Raymond, Jr. Joseph H.
Graham John G.
James Andrew J.
Texas Instruments Incorporated
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