Method for fabricating self-aligned, conformal metallization of

Details Method for fabricating self-aligned, conformal metallization of Method for fabricating self-aligned, conformal metallization of

1987-10-08

1988-08-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437201, 437195, 437192, 148DIG106, 148DIG20, H01L 2188, H01L 21302

Patent

active

047644842

ABSTRACT:
A method is disclosed for fabricating a VLSI multilevel metallization integrated circuit in which a first dielectric layer (10), a thin silicon layer (16), and then a second dielectric layer (18) are deposited on the upper surface of a substrate. A trench (20) is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole (26) is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion (24a) of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal (28) such as tungsten is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.

REFERENCES:
patent: 4582563 (1986-04-01), Hazuki et al.
patent: 4630537 (1986-12-01), Rogers et al.
patent: 4707218 (1987-11-01), Giammarco et al.

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