Method of manufacturing MOS transistor by dual species implantat

Details Method of manufacturing MOS transistor by dual species implantat Method of manufacturing MOS transistor by dual species implantat

1986-11-20

1988-08-16

Roy, Upendra

Fishing, trapping, and vermin destroying

437 24, 437 27, 437932, 437942, H01L 21265

Patent

active

047644788

ABSTRACT:
A semiconductor apparatus manufacturing method which is characterized in that the process of distributing an impurity in the gate electrode of the semiconductor apparatus is improved by the steps of depositing a gate oxide layer on a silicon substrate, mounting a polycrystalline silicon layer on said gate oxide layer, introducing boron as a first impurity in the surface of said polycrystalline silicon layer by the vapor phase diffusion process, solid phase diffusion process or ion implantation, ion-implanting arsenic or silicon, boron difluoride as a second impurity having a greater mass than the first impurity, and ensuring the uniform redistribution of the first impurity in the polycrystalline silicon layer by annealing or a Lamp Anneal process which is carried out at a low temperature and for a short time.

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Sodini, et al., "A JMOS Transistor Fabricated with 100-A Low-Pressure Nitrided-Oxide Gate Dielectric," IEEE Transactions on Electron Devices, vol. ED-31, No. 1, pp. 17-21, Jan. 1984.

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