Method of manufacturing a semiconductor device having multilayer

Fishing – trapping – and vermin destroying

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437238, 437231, 437195, H01L 2131, H01L 21316, H01L 21473, H01L, H01L

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054591058

ABSTRACT:
A method of manufacturing a semiconductor device having a flat surface and an interlayer insulating film having superior crack resistance comprises forming a first silicon oxide film having a superior crack resistance on a semiconductor substrate so as to cover the surface of a stepped pattern. A second silicon oxide film having a superior step coverage is deposited on the first silicon oxide film so as to fill the recessed portions of the stepped pattern and to cover the stepped pattern. The second silicon oxide film is etched to a prescribed thickness. A third silicon oxide film superior in filling of recesses is placed into the recessed portions existing on the surface of the second silicon oxide film after its etching. A fourth silicon oxide film is formed on the semiconductor substrate including the second silicon oxide film and third silicon oxide film.

REFERENCES:
patent: 4872947 (1989-10-01), Wang et al.
patent: 4894351 (1990-01-01), Chu et al.
patent: 4962063 (1990-10-01), Maydan et al.
patent: 4965226 (1990-10-01), Gootzen et al.
patent: 4972251 (1990-11-01), Lehrer
patent: 4983546 (1991-01-01), Hyun et al.
patent: 5079188 (1992-01-01), Kawai
patent: 5250472 (1993-10-01), Chen et al.
patent: 5252515 (1993-10-01), Tsai et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5393708 (1995-02-01), Hsia et al.
patent: 5403780 (1995-04-01), Jain et al.
`Planar Technique for Sub-Micron Device . . . `, Semiconductor News, 1989.6, Special Issue.
K. Fujino, `Silicon Dioxide Deposition by Atmospheric Pressure and Low-Temperature CVD . . . Ozone`, J. of Electrochemical Soc., vol. 137, No. 9, Sep. 1990, pp. 2883-2887.
Kenzo Matsuda and Keizo Sakiyama, "Planar Technique for Sub-Micron Device Planar Technique by Complex Process", Semicom News (Special Issue), Jun. 1989, pp. 62-67.
"Dielectric Film Deposition by Atmospheric Pressure and Low Temperature CVD Using TEOS, Ozone and New Organometallic Doping Sources", Nishimoto, et al., Jun. 1989, VMIC Conference, IEEE, pp. 382-389.
"A Single-pass, In-Suit Planarization Process Utilizing TEOS for Double-poly, Double-metal CMOS Technologies", Mehta et al., Jun. 1989, VMIC Conference, IEEE, pp. 80-88.
"Low-Temperature APCVD Oxide Using TEOS-ozone Chemistry for Multilevel Interconnections", Kotani et al., LSI Research and Development Laboratory, Mitsubishi Electric Corporation, pp. 28.2.1-28.2.4.
"Plasma TEOS Process for Interlayer Dielectric Applications", by B. L. Chin et al., Solid State Technology, Apr. 1988, pp. 119-122.
"Low-temperature APCVD Oxide Using TEOS-ozone Chemistry for Multilevel Interconnections", Kotani et al., LSI Research and Development Laboratory, Mitsubishi Electric Corporation, pp. 28.2.1-28.2.4.
"Comparison of Phosphosilicate Glass Films Deposited by Three Different Chemical Vapor Deposition Methods", by Toshimi Shioya et al., J. Electrochem. Soc.: Solid-State Science and Technology, Sep. 1986, vol. 133, No. 9, pp. 1943-1950.
"Stress in Silicon Dioxide Films Deposited Using Chemical Vapor Deposition Techniques and the Effect of Annealing On These Stresses", by Bharat Bhushan et al., J. Vac. Sci. Technol. B 8(5), Sep./Oct. 1990, pp. 1068-1074.
"Process Reliability Considerations of Planarization with Spin-on-Glass", by Yosi Shacham-Diamond, J. Electrochem. Soc., vol. 137, No. 1, Jan. 1990, pp. 190-196.
"Water-Related Degradation of Contacts in the Multilevel MOS IC with Spin-on Glasses as Interlevel Dielectrics", by N. Lifshitz et al., IEEE Electron Device Letters, vol. 10, No. 12, Dec. 1989, pp. 562-564.
"Application of Surface Reformed Thick Spin-on-Glass to MOS Device Planarization", by Shinichi Ito et al., J. Electrochem. Soc., vol. 137, No. 4, Apr. 1990, pp. 1212-1218.

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