Process for fabricating a semiconductor device using dual planar

Details Process for fabricating a semiconductor device using dual planar Process for fabricating a semiconductor device using dual planar

1994-07-05

1995-10-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 61, 437 42, 437 59, 437228, 148DIG5, 257370, 257506, H01L 21302

Patent

active

054590965

ABSTRACT:
An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.

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