Method for fabricating a capacitor cell in the semiconductor mem

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

054590949

ABSTRACT:
A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode. By the composite structure of the capacitor storage node including the lower structure having the cylinder shape and the cover type upper structure connected with the lower structure, it is possible to utilize efficiently a three-dimensional space structure and thereby achieve an increase in capacitance.

REFERENCES:
patent: 5049957 (1991-09-01), Inoue
patent: 5084405 (1992-01-01), Fazan et al.
patent: 5219780 (1993-06-01), Jun
patent: 5274258 (1993-12-01), Ahn

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