Fishing – trapping – and vermin destroying
Patent
1993-08-03
1995-10-17
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437184, 437192, H01L 21265, H01L 2144, H01L 2148
Patent
active
054590876
ABSTRACT:
The invention provides a method of forming a gate electrode on a channel layer in a field effect transistor. A first layer made of a first metal having a heat resistivity is formed on a gate formation region of a surface of a channel layer on a semiconductor substrate. The substrate is subjected to a heat treatment so as to recover a damage of the channel layer caused by the formation of the first layer. A second layer made of a second metal having a heat resistivity is formed on a surface of the first layer. A third layer made of a third metal having a low electrical resistivity is formed on a surface of the second layer thereby a gate electrode comprising the first, second and third layers is formed on the channel layer free from any damage caused by the formation steps.
REFERENCES:
patent: 4638551 (1987-01-01), Einthoven
patent: 4923823 (1990-05-01), Kohno
patent: 4927782 (1990-05-01), Davey et al.
patent: 5032541 (1991-07-01), Sakamoto et al.
patent: 5087950 (1992-02-01), Katano
patent: 5143856 (1992-09-01), Iwasaki
patent: 5155053 (1992-10-01), Atkinson
patent: 5278099 (1994-01-01), Maeda
patent: 5358885 (1994-10-01), Oku et al.
"Schottky barriers on ordered and disordered surfaces of GaAs(110)", J. Vac. Sci. Technol., vol. 15, No. 4, Jul./Aug., 1978, By A. Amith et al., pp. 1344-1352.
"Sputtered Schottky barrier solar cells on p-type GaAs", Appl. Phys. Lett., vol. 43, No. 6, Sep. 15, 1983, By M. Edweeb et al., pp. 572-574.
"Electrical characterization of Schottky contacts of Au, Al, Gd, and Pt on n-type and p-type GaAs", J. Appl. Phys., vol. 61, No. 8, Apr. 15, 1987, By T. Okumura et al., pp. 2955-2961.
Wolf, Stanley and Richard Tauber, "Silicon Processing For The VLSI Era", Lattice Press, Sunset Beach, Calif., vol. 1, 1986.
Wolf, Stanley, "Silicon Processing for the VLSI Era", Lattice Press, Sunset Beach Calif., vol. 2, 1990.
Chaudhuri Olik
Dutton Brian K.
NEC Corporation
LandOfFree
Method of fabricating a multi-layer gate electrode with annealin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a multi-layer gate electrode with annealin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a multi-layer gate electrode with annealin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-596922