Method for making BIMOS device having a bipolar transistor and a

Details Method for making BIMOS device having a bipolar transistor and a Method for making BIMOS device having a bipolar transistor and a

1993-03-01

1995-10-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 6, 437 59, 437 61, 437 63, 437 64, 148DIG9, 257141, 257370, 257378, H01L 21265

Patent

active

054590833

ABSTRACT:
The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

REFERENCES:
patent: 4353085 (1982-10-01), Sakurai
patent: 4697199 (1987-09-01), De Graaff et al.
patent: 4786958 (1988-11-01), Bhagat
patent: 4971921 (1990-11-01), Fukunaga et al.
patent: 5043782 (1991-08-01), Avery
patent: 5124271 (1992-06-01), Havemann
"Lateral Junction--Isolated Emitter Switched Thyrister", B. Joyant Baliga et al., IEEE EDL vol. 13, No. 12, Dec. 1992.
"Investigation of . . . With a Buried Drain", Marius Orlowski, IEEE, 1992.
"Snap-Back . . . " A. Ochoa et al. MOS-Controlled Thyristors . . . , Victor Temple, IE.sup.3 To Ed, ED-33. No. 10. Oct. 1986.
"The Insulated Gate . . . Power Device", Baliga et al., IE.sup.3 TOED, vol. ED-31, No. 6 Jun. 1984.
Orlowski, et al.; "Investigation of SOI-Like I-V Characteristics for a 64-Mb Dram SCC MOSFET with a Buried Drain", IEEE Trans. on Electron Devices; vol. 39, No. 7, pp. 1652-1660 (Jul. 1992).
Ochoa, et al.; "Snap-Back:A Stable Regenerative Breakdown Mode of MOS Devices", Sandia Nat'l Lab., Contract No. DE-ACO4-76DP00789 (1983).
Victor A. K. Temple; "MOS-Conrolled Thyristors-A New Class of Power Devices"; IEEE Trans. on Elecron Devices; vol. ED-33, No. 10, pp. 1609-1618 (1986).
Baliga, et al.; "The Insulated Gate Transistor: A New Three-Terminal MOS Controlled Bipolar Power Device", IEEE Trans. on Electron Devices; vol. ED-31, No. 6, pp. 821-828 (1984).

Affiliated with

Also associated with

Rating

Method for making BIMOS device having a bipolar transistor and a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making BIMOS device having a bipolar transistor and a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making BIMOS device having a bipolar transistor and a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-596854