Method for producing a semiconductor layer structure having a pl

Details Method for producing a semiconductor layer structure having a pl Method for producing a semiconductor layer structure having a pl

1994-07-22

1997-07-01

Chu, John S.

Fishing, trapping, and vermin destroying

437235, 437238, H01L 21465

Patent

active

056438362

ABSTRACT:
An insulating layer is applied onto the surface of a semiconductor layer structure having elevations up to a maximum step height. The thickness of the insulating layer is greater than the maximum step height. The insulating layer is structured to have irregularities with an essentially identical lateral expanse in the region of the edges of the elevations. The irregularities are planarized by chemical mechanical polishing and/or by deposition, flowing and etch-back of a planarization layer.

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