Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1995-03-13
1996-10-08
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257786, 257693, H01L 2348, H01L 2352, H01L 2304
Patent
active
055634451
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of technology
This invention relates to a semiconductor device, particularly one with a structure suitable for the assembly of a relatively large-sized semiconductor chip, and a structure suitable for the assembly of a semiconductor chip onto a flexible circuit board that is often used in quartz watch applications.
2. Background Technology
In the assembly of a semiconductor chip onto a circuit board, such as shown in FIG. 7, a molding agent 55 is injected through a device hole 53, after the lead 521 of the conductive pattern 52 formed on the circuit board 51, which protrudes into the device hole 53, is bonded to the bump 541 of the semiconductor chip 54. This lead 521 is usually formed downward to prevent short-circuiting between the edge of the semiconductor chip 54 and the conductive pattern 52.
However, in this type of assembly structure, the lead 521 is bent to a great degree, with the result of increasing the thickness of the semiconductor device. Furthermore, during the lead-forming process, increases in the number of leads 521 also result in increases in the irregularity of the shape and position of each lead. Consequently, in the assembly of a large-sized semiconductor chip 54, these forming-related irregularities result in some of the bumps 541 not being bonded to the leads 521. Furthermore, the device hole 55 must be enlarged as the size of the semiconductor chip 54 increases, thus increasing the planar area of the semiconductor device. For this reason, this assembly method cannot be used in electronic instruments, such as quartz watches, which require small size.
One possible method of increasing stability against warpage, etc., in the assembly of a large-size semiconductor chip 54, is as follows. Reinforcing dummy bumps, which are electrically insulated from the internal circuit, are formed on the side of the semiconductor chip 54. Bonding in the additional areas made available by these dummy bumps is used to increase the bonding strength between the semiconductor chip 54 and the circuit board 52. However, the dummy bump connection used in this type of structure also requires a forming process, and thus the above-mentioned problems associated with the forming process cannot be eliminated.
Another assembly structure suitable for achieving thin semiconductor device profile uses a method in which a solder bump 62 formed on the semiconductor chip 61 is heated under pressure and bonded with the conductive pattern 64 of the circuit board 63, as shown in FIG. 8. In this type of assembly structure, because part of the circuit board 63 overlaps the active area of the semiconductor chip 61, the conductive pattern 64 can also be formed in this overlapping area. This results in a high degree of pattern design freedom, which is suitable to achieving thin semiconductor device profile. However, the solder bump 62 does require a complicated manufacturing process, thus resulting in high manufacturing cost. Furthermore, because the semiconductor chip 61 must be heated first and then cooled during the process of assembling the semiconductor chip 61 onto the circuit board 63, the resulting long manufacturing throughput makes it difficult to reduce costs.
In an assembly structure using this kind of solder bump 62, possible methods of preventing short-circuiting between the circuit board 63 and the semiconductor chip 61 include increasing the thickness of the solder bump 62, or forming dummy solder bumps. However, as long as solder bumps are used, the above-mentioned manufacturing-related problem will remain.
In order to solve these problems, the invention is intended to provide thinner-profile, lower-cost semiconductor devices, while achieving reliability superior to that attainable using conventional assembly structures, even when single-point or gang bonding methods are used. Additionally, the invention is intended to provide semiconductor devices with improved pattern design freedom.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, the invention is
REFERENCES:
patent: 3871015 (1975-03-01), Lin et al.
patent: 5186383 (1993-02-01), Melton et al.
patent: 5198963 (1993-03-01), Gupta et al.
patent: 5400950 (1995-03-01), Myers et al.
Iijima Yoshitaka
Seki Shigeaki
Clark S. V.
Janofsky Eric B.
Saadat Mahshid
Seiko Epson Corporation
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