Method for forming trench-isolated FET devices

Details Method for forming trench-isolated FET devices Method for forming trench-isolated FET devices

1995-01-10

1997-07-01

Niebling, John

Fishing, trapping, and vermin destroying

437 34, 437 57, 437 58, H01L 2176

Patent

active

056438222

ABSTRACT:
A method for improving the subthreshold leakage characteristics of a trench-isolated FET device is described. This method involves first forming a vertical slot within a stack structure disposed on an oxide-covered silicon substrate, and then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate. Removal of the spacers uncovers a horizontal ledge on the exposed surfaces of the oxide-covered substrate, adjacent the trench. The ledge is then perpendicularly implanted with a suitable dopant, thereby suppressing edge conduction in the device. Articles prepared by this method are also described.

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