Method of fabricating fork-shaped stacked capacitors for DRAM ce

Details Method of fabricating fork-shaped stacked capacitors for DRAM ce Method of fabricating fork-shaped stacked capacitors for DRAM ce

1995-10-30

1997-07-01

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437191, 437919, H01L 218242

Patent

active

056438192

ABSTRACT:
A method for manufacturing an array of fork-shaped stacked capacitors with increased capacitance on a dynamic random access memory (DRAM) device, was achieved. The invention utilizes a single masking step and self-aligning etch back steps to form a very high density array of bottom capacitor (node) electrodes for a DRAM device. The method involves depositing and planarizing a thick insulating over the DRAM cell areas, and then etching node contact openings with vertical sidewalls to the node contact areas of the FETs. Polysilicon plugs are formed in the node contact openings, and then the thick insulating layer is etched back to expose the upper portion of the plugs. Another polysilicion layer is deposited and then silicon nitride sidewall spacers followed by polysilicon sidewall spacers are formed by etch back to provide fork-shaped bottom electrodes. After removing the silicon nitride spacers, a capacitor interelectrode dielectric is formed on the bottom electrodes and another polysilicon layer is patterned to form the top electrodes and complete the array of fork-shaped storage capacitors on the DRAM device.

REFERENCES:
patent: 5332685 (1994-07-01), Park et al.
patent: 5364813 (1994-11-01), Koh
patent: 5386382 (1995-01-01), Ahn
patent: 5399518 (1995-03-01), Sim et al.
patent: 5491103 (1996-02-01), Ahn et al.
patent: 5519719 (1996-05-01), Ryou

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