Sequential chip select decode apparatus and method

Details Sequential chip select decode apparatus and method Sequential chip select decode apparatus and method

1980-01-08

1982-04-06

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

043239650

ABSTRACT:
A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.

REFERENCES:
patent: 3440615 (1969-04-01), Carter
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4236203 (1980-11-01), Curley et al.

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