Non-uniform memory access (NUMA) data processing system with mul

Details Non-uniform memory access (NUMA) data processing system with mul Non-uniform memory access (NUMA) data processing system with mul

1998-12-17

2000-08-22

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

710104, 711119, 711122, 711130, 711141, G06F 1516

Patent

active

061087645

ABSTRACT:
A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are coupled together. The first processing node includes a system memory and first and second processors that each have a respective associated cache hierarchy. The second processing node includes at least a third processor and a system memory. If the cache hierarchy of the first processor holds an unmodified copy of a cache line and receives a request for the cache line from the third processor, the cache hierarchy of the first processor sources the requested cache line to the third processor and retains a copy of the cache line in a Recent coherency state from which the cache hierarchy of the first processor can source the cache line in response to subsequent requests.

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