Method and apparatus for concurrency of bus operations

Details Method and apparatus for concurrency of bus operations Method and apparatus for concurrency of bus operations

1992-10-02

1994-10-04

MacDonald, Allen R.

Boots, shoes, and leggings

395425, 3649646, 364964341, 364964342, 364DIG2, G06F 1300

Patent

active

053534158

ABSTRACT:
A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.

REFERENCES:
patent: 4261034 (1981-04-01), Saccomano et al.
patent: 4571672 (1986-02-01), Hatada et al.
patent: 4920486 (1990-04-01), Nielsen
patent: 4987529 (1991-01-01), Craft et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5157774 (1992-10-01), Culley
patent: 5195089 (1993-03-01), Sindhu et al.
patent: 5228135 (1993-07-01), Ikumi
J. Cantrell, Futurebus+ Cache Coherence, Ire Wescon Convention Record, vol. 34, Nov. 1990, pp. 90-94.
J. Gallant, Futurebus+, EDN Electrical Design News, vol. 35, No. 20, Oct. 1990, pp. 87-94, 96, 98.
82495XP Cache Controller/82490XP Cache RAM Data Manual, Intel Corp. 1991, pp. 1-7, 11-34, 43-92.

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