Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-02-04
2000-08-22
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518526, G11C 1604
Patent
active
061082406
ABSTRACT:
A method and apparatus for erasing a single floating gate transistor in an array of floating gate transistors is provided. A selected floating gate transistor, which is located in a first row and a first column of the array, is erased as follows. A low voltage V.sub.LOW (e.g., 0 Volts) is applied to the gate of each transistor in the first row of the array. An erase voltage V.sub.ERASE (e.g., 8 Volts) is applied to the drain of each transistor in the first column of the array. An intermediate voltage V.sub.INT (e.g., 3 Volts) is applied to the source of each transistor in the array, as well as to the drain of each transistor of the array that is not in the first column. Under these conditions, only the selected floating gate transistor is erased. Other floating gate transistors in the first column are not erased because the gate-to-drain voltages of these transistors are limited by the intermediate voltage V.sub.INT applied to their gates.
REFERENCES:
patent: 4366555 (1982-12-01), Hu
patent: 5199001 (1993-03-01), Tzeng
patent: 5764572 (1998-06-01), Hammick
patent: 5768192 (1998-06-01), Eitan
patent: 5838626 (1998-11-01), Nakayama
Dadashev Oleg
Lavi Yoav
Hoffman E. Eric
Lam David
Nelms David
Tower Semiconductor Ltd.
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