Memory integrated circuit with balanced resistance

Details Memory integrated circuit with balanced resistance Memory integrated circuit with balanced resistance

1993-08-24

1994-10-04

LaRoche, Eugene R.

Static information storage and retrieval

Interconnection arrangements

365154, 365182, 257395, 257963, 257904, G11C 1140, H01L 2702

Patent

active

053532457

ABSTRACT:
An integrated circuit, illustratively an SRAM, with pull down gates symmetrically positioned with respect to the ground line is disclosed. The symmetric positioning helps to insure cell stability.

REFERENCES:
patent: 4459687 (1984-07-01), Shiotari et al.
patent: 4535426 (1985-08-01), Ariizumi et al.
patent: 4740825 (1988-04-01), Saeki
patent: 4794561 (1988-12-01), Hsu
patent: 4797717 (1989-01-01), Ishibashi

Affiliated with

Also associated with

Rating

Memory integrated circuit with balanced resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory integrated circuit with balanced resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory integrated circuit with balanced resistance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-586440