Memory array unit for computer

Details Memory array unit for computer Memory array unit for computer

1989-03-24

1989-11-28

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1300, G06F 1200, G11C 1300

Patent

active

048841919

ABSTRACT:
The computer (10) includes a memory control unit (12), a central processing unit (14) and a memory array unit (16). A plurality of memory array planes (36, 38, 40 and 42) are included within the memory array unit (16). A latch (82) receives write data from the memory control unit (12) through a bus (26). Address and control information is transferred from the memory control unit (12) to timing and address circuits (28, 30, 32, 34). The write data is transferred from the latch (82) into a selected one of the memory array planes (36, 38, 40, 42). For each of the memory array planes (36, 38, 40, 42) there is provided a respective read latch (60, 62, 64, 66) for receiving read data. The ouputs of the memory array planes are not connected in common. The ouputs to read latches (60, 62, 64,66) are connected in common through a bus (76) for transferring read data through the data bus (26) back to the memory control unit (12). The memory array unit (16) provides enhanced speed of operation for the computer (10) while permitting refresh interrupts to occur without loss of read or write data.

REFERENCES:
patent: 4101960 (1978-07-01), Stokes et al.
patent: 4172282 (1979-10-01), Aichelmann, Jr. et al.
patent: 4236207 (1980-11-01), Rado et al.
patent: 4400768 (1983-08-01), Tomlinson
Mostek, "Memory Designers Guide", Jul. 1982.
Chu, Y., Computer Organization and Micro-Programming, 1972, Chap. 7.

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