High speed comparator with programmable reference

Details High speed comparator with programmable reference High speed comparator with programmable reference

1996-11-12

1998-05-05

Wambach, Margaret Rose

Communications: electrical

Digital comparator systems

G06F 702

Patent

active

057480710

ABSTRACT:
A system rapidly dynamic values (B) on a bus (12) to a programmable but thereafter fixed reference value (C). The system includes first leads (33) coupled to a comparison means (35), second leads (13) coupled to the bus (12) and third leads (34, 36) coupled to sources of potential (GND, VCC) related to logical HIGH and LOW of the fixed reference value (C). The leads (33, 13, 34, 36) are coupled in one or more programmable connection cell (32). Connections (471) or disconnections (461) are made between the leads (33, 13, 34, 36) so that the dynamic values (B) and the appropriate logical HIGH and logical LOW values are presented to the correct inputs of the comparison means (35). The programmable connections cells (32) invert the reference value (C) to (C) for coupling to the comparator (35). The system replaces a level of conventional decode logic (16) by the programmable interconnections (47), thereby reducing delay time, using fewer devices and occupying less circuit area.

REFERENCES:
patent: 4857882 (1989-08-01), Wagner et al.
patent: 5581228 (1996-12-01), Cadieux et al.
patent: 5586288 (1996-12-01), Dahlberg

Affiliated with

Also associated with

Rating

High speed comparator with programmable reference does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed comparator with programmable reference, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed comparator with programmable reference will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-58598