Method and direct memory access controller for asynchronously re

Details Method and direct memory access controller for asynchronously re Method and direct memory access controller for asynchronously re

1991-10-17

1994-02-01

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 364239, 36424231, 395250, G06F 1300, G06F 1328, G06F 1336

Patent

active

052838838

ABSTRACT:
Buffer lines and corresponding buffer tags and buffer valid/dirty registers in conjunction with buffer control circuit are provided to a DMA controller enabling the DMA controller to conditionally pre-fetch data from memory while data being read are transferred from the DMA controller to the I/O device during read operations and to conditionally write data back to memory while data being written are transferred from the I/O device to the DMA controller during write operations, thereby improving asynchronous read/write throughputs. Read requests, random as well as sequential, are satisfied with pre-fetched data if they are validly stored. Write requests, random as well as sequential, are deferred, batched and optimized. The improved throughput is achieved in a manner completely transparent to system software.

REFERENCES:
patent: 4910656 (1990-03-01), Scales, III, et al.
patent: 5019962 (1991-05-01), Funabashi et al.
patent: 5175818 (1992-12-01), Kunimoto et al.
patent: 5179663 (1993-01-01), Iimura
patent: 5182800 (1993-01-01), Farrell et al.
Computer Design, vol. 24, No. 8, Published Jul. 1985, in Littleton, Mass., USA, pp. 85-88, Author: Michael M. Tehranian, Entitled: DMA Cache Speeds Execution in Mixed-Bus Systems.
Microprocessors and Microsystems, vol. 14, No. 10, Published Dec. 1990, London GB, pp. 653-663, Entitled: Enhancing MC68030 performance using the SN74ACT2155 Cache.
IBM Technical Disclosure Bulletin, vol. 31, No. 11, Published Apr. 1989, Armonk, N.Y., U.S., pp. 324-328, Entitled: Direct Memory Access For Multiple Requesting Computer Devices.
IBM Technical Disclosure Bulletin, vol. 33, No. 1A, Published Jun. 1990, Armonk, N.Y., U.S., pp. 41-43, Entitled: Direct Memory Access Transfer Control Technique.

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