Power up/power down controller and power fail detector for proce

Details Power up/power down controller and power fail detector for proce Power up/power down controller and power fail detector for proce

1990-10-19

1994-02-01

Beausoliel, Jr., Robert W.

Excavating

395575, G06F 1100

Patent

active

052837920

ABSTRACT:
A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail situation and output an interrupt to the CPU (10). The CPU (10) then goes into a power down sequence and stores critical instructions in an internal memory array (30) constituting a hidden memory during the power down sequence. An out of tolerance detector detects when the power supply voltage has fallen below a predetermined threshold and then generates reset signal. The reset signal is input to the CPU (10) to indicate that no further instructions are executable. In addition, a Chip Enable switch (46) is operated to inhibit memory control signals from being transferred from the CPU (10) to the memory (16). The internal hidden memory (30) is also inhibited from having data written thereto in the presence of the reset signal. A backup battery (22) is provided which is connected to one side of a switch. The other side of the switch is connected to the power supply voltage. When the power supply voltage falls below the battery voltage, the battery is connected to supply a current to the external memory (16).

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