Multiplier employing carry select or carry look-ahead adders in

Details Multiplier employing carry select or carry look-ahead adders in Multiplier employing carry select or carry look-ahead adders in

1993-04-14

1994-02-01

Mai, Tan V.

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364758, G06F 752

Patent

active

052837556

ABSTRACT:
A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of an M bit multiplicand and an N bit multiplier. The partial products generator outputs to the carry adder circuit partial products based on the M bit multiplicand and N bit multiplier. The carry adder circuit contains a plurality of carry adders connected in a hierarchical tree structure such that a plurality of carry adder stages are defined, with each carry adder stage except a first carry adder stage receiving adder sums from a next adjacent, lower carry adder stage in the hierarchical tree structure. The first carry adder stage receives the partial products output from the partial products generator. The multiplication circuit is optimized by employing carry select adders or carry look-ahead adders in the hierarchical tree structure.

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Gosling, John B., "Design of Arithmetic Units for Digital Computers", pp. 8-14, 1980.
Habibi and Wintz, "Fast Multiplier" IEEE Transaction on Computer, pp. 154-157, Feb. 1970.

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