Compliant wirebond packages having wire loop

Details Compliant wirebond packages having wire loop Compliant wirebond packages having wire loop

1999-09-01

2000-08-22

Graybill, David E.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257696, 257702, 257773, 257778, 257779, 257784, 257787, H01L 2348, H01L 2314, H01L 2352, H01L 2940, H01L 2328

Patent

active

061076821

ABSTRACT:
A semiconductor chip assembly with a frame having an aperture, a continuous rail enclosing the aperture and bonds pads disposed on the top surface of the continuous rail; a semiconductor chip having contacts on its top surface fitted within the aperture; a plurality of wire loops connecting the bond pads to the contacts, and a compliant layer disposed over the first surface of the semiconductor chip and the plurality of wire loops such that the top portion of each wire loop is exposed. The semiconductor chip assembly can be incorporated into a larger assembly by connecting the wire loops to connection pads on an external substrate.

REFERENCES:
patent: 4764848 (1988-08-01), Simpson
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5455390 (1995-10-01), DiStefano et al.
patent: 5476211 (1995-12-01), Khandros
patent: 5801446 (1998-09-01), DiStefano
patent: 5806181 (1998-09-01), Khandros
patent: 5829128 (1998-11-01), Eldridge et al.

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