Trigger circuit for a power FET with a load on the source side

Details Trigger circuit for a power FET with a load on the source side Trigger circuit for a power FET with a load on the source side

1993-06-07

1994-10-04

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307574, H03K 19094, H03K 17687

Patent

active

053529324

ABSTRACT:
A first power FET has a source terminal, a gate terminal and a drain terminal and a load is connected in series with the source terminal of the power FET. A circuit configuration for triggering the first power FET includes a first input terminal. A first diode and a capacitor are connected between the first input terminal and the gate terminal of the first power FET. A second FET of the opposite channel type from that of the first power FET has a gate terminal and has drain and source terminals defining a drain-to-source path. A second diode is connected between the first diode and the capacitor and is connected through the drain-to-source path of the second FET to the drain terminal of the power FET. A resistor is connected between the gate and source terminals of the second FET. A controllable switch is connected to the gate terminal of the second FET. A second input terminal is connected to the controllable switch for receiving a voltage being lower than a supply voltage. A third depletion FET has a gate terminal connected to the controllable switch and has drain and source terminals defining a drain-to-source path connected between the gate terminal and the source terminal of the first power FET for discharging a gate-to-source capacitance of the first power FET.

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IBM Technical Disclosure Bulletin, vol. 26, No. 6 Nov. 1983.
BiDirectional Bipolar Electronic Switch, M. M. Bhansali, C. Munoz-Bustamante, and W. N. Zalph.

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