Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1998-07-06
2000-08-22
Booth, Richard
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438113, 438612, H01L 2144, H01L 2148, H01L 2150
Patent
active
061071196
ABSTRACT:
A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.
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Farnworth Warren M.
Wood Alan G.
Booth Richard
Gratton Stephen A.
Jones Josetta
Micro)n Technology, Inc.
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