High performance FET driver circuit

Details High performance FET driver circuit High performance FET driver circuit

1981-04-16

1985-01-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307482, 307463, 307578, 307270, H03K 19017, H03K 19096, H03K 1704, G11C 800

Patent

active

044917481

ABSTRACT:
An FET high performance driver circuit which is especially effective in an environment wherein both large input and output capacitive loads are present is described. The driver features a push-pull output circuit, a clocked load, and a switched transfer depletion FET adapted to decouple the large input capacitive load from an internal node of the driver circuit. This switched decoupling allows an isolation of the large input capacitance from the internal node, whereby the internal node potential can be raised rapidly, and the bootstrapping effectiveness at the internal node can be enhanced so as to significantly increase the circuit operating speed in driving large output capacitive loads.

REFERENCES:
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patent: 3995171 (1976-11-01), Sonoda
patent: 4065678 (1977-12-01), Reese et al.
patent: 4071783 (1978-01-01), Knepper
patent: 4081699 (1978-03-01), Hirt et al.
patent: 4135102 (1979-01-01), Green et al.
patent: 4307308 (1981-12-01), Sano
patent: 4381460 (1983-04-01), Menachem
Patel, "Precharge for Bootstrap Circuit", IBM Tech. Discl. Bull., vol. 20, No. 7, pp. 2748, 12/77.
Love, "In-Phase Weak-Signal Input Circuit", IBM Tech. Discl. Bull., vol. 19, No. 12, pp. 4673, May 1977.
Hardee et al., a preprint article entitled, "A 30ns/375mW 16K.times.1 Static MOS RAM", submitted on or about Oct., 1980 to the Feb., 1981 ISSCC.
Takahashi et al., article entitled, "High Speed 4k Static RAM Using DAS MOST's" Proceedings of the 9th Conference on Solid State Devices, Tokyo, 1977.

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