1997-05-29
1998-03-31
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
057346623
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a period generating device which is used in a semiconductor device testing apparatus (commonly called IC tester) for testing a semiconductor device, particularly, a semiconductor integrated circuit element (hereinafter referred to as IC) which is a typical example of the semiconductor devices, and generates a pulse signal having a test period which is previously set, that is, a pulse having a period with which a test pattern is generated.
BACKGROUND ART
First, a semiconductor device testing apparatus (hereafter referred to as IC tester) in which a period generating device of this type is used will be briefly described with reference to FIG. 4 which shows a general arrangement of a conventional IC tester. The IC tester, generally designated by reference numeral 1, comprises, roughly speaking, a timing generator (TMG GEN) 2 for generating various kinds of timing signals, a pattern generator (PTN GEN) 3 supplied from the timing generator 2 with a timing signal (TMG SIG), that is, a period signal (PRD SIG) defining the period with which a test pattern is generated and for generating a predetermined test pattern data (TEST PTN DATA) in accordance with the period signal, a waveform generator (WAVE GEN) 4 for generating a test pattern signal (TEST PTN SIG) having real waveforms required to test an IC 6 to be tested based on the test pattern data supplied from the pattern generator 3, and a logical comparator (LG COMPA) 5 to which a response output signal (RPS OUT SIG) from the IC 6 to be tested and an expected pattern data (EP PTN DATA) generated from the pattern generator 3 are supplied.
A response output signal outputted from the IC 6 to be tested in response to a test pattern signal applied from the waveform generator 4 is inputted to the logical comparator 5 wherein it is logically compared with an expected value pattern data outputted from the pattern generator 3. When the response output signal does not coincide with the expected value pattern data, the logical comparator 5 generates a signal indicating that there is an anti-coincidence therebetween so that a decision is rendered that the IC to be tested contains a defective portion (failure) or portions.
The period of a period signal outputted from the timing generator 2 is defined by timing set data (TMG SET DATA) TS which is fed from the pattern generator 3 to the timing generator 2. That is, the timing generator 2 outputs a period signal the period of which is defined depending upon the timing set data TS outputted from the pattern generator 3, and the pattern generator 3 outputs test pattern data in accordance with the period of that period signal.
A general arrangement of a conventional period generating device which defines the period of a period signal will now be described with reference to FIG. 5. As shown in FIG. 5, a period generating device 10 is provided within the timing generator 2, and may comprise a period memory (PRD MEM) 11 in which period data are previously stored, a counter (CTR) 12 for counting a reference clock (REF CLK) PC used in the period generating device 10, and coincidence detecting means 13 for outputting a coincidence detection signal J when a count value of the counter 12 coincides with period data outputted from the period memory 11.
The timing set data TS outputted from the pattern generator 3 is inputted to an address terminal of the period memory 11 thereby reading out of the period memory 11 period data corresponding to respective timing set data TS. A period data which is read out of the period memory 11 corresponds to the number of reference clocks PC. For example, if the reference clock PC has a frequency of 100 MHz, one period of the reference clock is equal to 10 nanoseconds (nsec). Accordingly, when a period data read out of the period memory 11 in response to the inputted timing set data TS is equal to, for example, "2" (which indicates that the number of the reference clocks is equal to 2), the outputted period signal has a period of 2.times.10 (=20) nsec. I
Advantest Corporation
Canney Vincent P.
LandOfFree
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