Method for suppressing charge loss in EEPROMs/EPROMS and instabi

Details Method for suppressing charge loss in EEPROMs/EPROMS and instabi Method for suppressing charge loss in EEPROMs/EPROMS and instabi

1992-03-30

1994-03-01

Thomas, Tom

Fishing, trapping, and vermin destroying

437 40, 437 43, 437 48, 437235, 437238, H01L 2170

Patent

active

052907279

ABSTRACT:
Suppression of charge loss and hot carrier degradation in EEPROMs and EPROMs, and of instability in the polysilicon pull-up resistors associated with SRAMs is achieved by the inclusion of at least one layer of silicon-enriched oxide in the MOS structure. In such MOS structures, the silicon-enriched oxide layer may be disposed immediately beneath the interlayer dielectric layer, or immediately beneath the inter-metal oxide layer, or immediately beneath the passivation layer, or in any combination of these locations. Each silicon-enriched oxide layer preferably contains at least about 10.sup.17 per cm.sup.3 dangling bonds.

REFERENCES:
patent: 4398335 (1983-08-01), Lehrer
patent: 4458407 (1984-07-01), Hoeg, Jr. et al.
patent: 4717943 (1988-01-01), Wolf et al.
patent: 4764484 (1988-08-01), Mo
patent: 4810673 (1989-03-01), Freeman
patent: 5057897 (1991-10-01), Nariani et al.
S. Yoshida et al. "Improvement of Enourance to Hot Carrier Degradation by Hydrogen Blocking P-510" IEDM 1988 pp. 22-25.

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