Semiconductor chip package with enhanced thermal conductivity

Details Semiconductor chip package with enhanced thermal conductivity Semiconductor chip package with enhanced thermal conductivity

1996-06-27

1998-05-05

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

257706, 257720, H01L 2306

Patent

active

057478775

ABSTRACT:
A semiconductor chip package and method of making same wherein the package comprises a ceramic substrate having two layers of thermally and electrically conductive material (e.g., copper) on opposing surfaces thereof, these layers thermally and electrically coupled by metal material located within holes provided in the ceramic. A semiconductor chip is mounted on one of these layers and the contact sites thereof electrically coupled to spaced circuitry which, in a preferred embodiment, Is formed simultaneously with both thermally conductive layers. Coupling of the circuitry to an external substrate (e.g., printed circuit board) is preferably accomplished using metallic spring clips. These clips are preferably soldered in position. A preferred metal for being positioned within the hole(s) is solder, one example being 10:90 tin: lead solder. The package as produced herein may further include two quantities of a protective encapsulant material located substantially on the upper portions thereof to protect the chip and circuitry. The preferred means for coupling the chip to the circuitry is to use a wire bonding operation.

REFERENCES:
patent: 4396936 (1983-08-01), McIver et al.
patent: 5113315 (1992-05-01), Capp. Michael et al.
patent: 5406120 (1995-04-01), Jones

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