Hybrid execution unit for complex microprocessor

Details Hybrid execution unit for complex microprocessor Hybrid execution unit for complex microprocessor

1996-02-15

1996-11-12

Donaghue, Larry D.

Boots, shoes, and leggings

395376, 364DIG7, 36493111, 36493152, 3649311, 3649336, 36493362, G06F 930

Patent

active

055749429

ABSTRACT:
A hybrid execution unit for executing miscellaneous instructions in a single clock cycle. The execution unit receives either integer or floating point data, and performs manipulations of two incoming sources to produce a result source in conjunction with existing integer and floating point execution units.

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Popescu, et al., "The Metaflow Architecture," IEEE Micro, pp. 10-13 and 63-73, Jun. 1991.
Intel, "i750, i860, i960 Processors and Related Products", 1993, pp. 2-1-2-47 and pp. 3-234-3-245.
Pleszkun et al. "WISQ: A Restartable Architecture Using Queues" 1987.
Gillom et al.; "Design and Architecture for a Multi-Mode Pipelined, Floating Point Adder", 73-76, Feb. 1991.
Mahon et al. "Hewlett-Packard Precision Architecture: The Processor"; 4-22; Aug. 1986.
Patt et al., "HPS, A New Microarchitecture: Rationale and Introduction"; 103-108; 1985.

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