Boots – shoes – and leggings
Patent
1994-10-26
1996-11-12
Bowler, Alyssa H.
Boots, shoes, and leggings
39520015, 395850, 395853, 395872, 36423222, 36423291, 364DIG1, G06F 300
Patent
active
055749330
ABSTRACT:
A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an instruction, a data element, and a pointer to another memory packet. Tasks are executed by following a linked list of memory packets. Transmission packets communicate instructions and register values along the linked list. A plurality of computer processes may be executed simultaneously.
REFERENCES:
patent: 3962706 (1976-06-01), Dennis et al.
patent: 4149240 (1979-04-01), Misunas et al.
patent: 4153932 (1979-05-01), Dennis et al.
patent: 4837676 (1989-06-01), Rosman
patent: 4893234 (1990-01-01), Davidson et al.
patent: 4972315 (1990-11-01), Yamasaki et al.
patent: 5021947 (1991-06-01), Campbell et al.
patent: 5043880 (1991-08-01), Yoshida
patent: 5093919 (1992-03-01), Yoshida et al.
patent: 5095480 (1992-03-01), Fenner
patent: 5117489 (1992-05-01), Komori et al.
patent: 5133062 (1992-07-01), Joshi et al.
patent: 5179685 (1993-01-01), Nojiri
Jain et al., "WSI Architecture for L-V Decomposition: A Radar Array Processor", IEEE Feb. 1990, pp. 102-108.
Ramaswamy et al., "A Methodology for Wafer Scale Integration of Linear Pipelined Arrays", IEEE Feb. 1990, pp. 220-228.
Bowler Alyssa H.
Nguyen Dzung C.
Tandem Computers Incorporated
LandOfFree
Task flow computer architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Task flow computer architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Task flow computer architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-572584