Patent
1994-06-17
1996-11-12
Ray, Gopal C.
395726, G06F 946, G06F 1500
Patent
active
055749224
ABSTRACT:
A system and method for executing sequences of instructions which can be used to access a memory location in a locked fashion. The first instruction specifies an address and sets a lock register which disables interrupts until it is cleared. The second instruction specifies an address and clears the lock register. The second instruction is not executed if the lock register was already cleared and doesn't update memory if the cache line of the first address is no longer valid. If the second address is not cacheable, the instructions are off-loaded to the bus interface and the results of the update are used to update the processor state. The present invention allows locked memory updates and process synchronization without locking of arbitrary duration of the entire shared data structure. The calculation and update of the data structure may continue after a context switch. The present invention is compatible with a wide range of cache-coherence protocols.
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Micro Soft Press Computer Dictionary 1994 Page 30.
J. M. Stone, et al., "Multiple Reservations and the Oklahoma Update," IEEE Parallel & Distributed Technology, Nov. 1993, pp. 58-71.
Apple Computer Inc.
Larwood David J.
Myers Paul R.
Ray Gopal C.
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