DRAM control circuit

Details DRAM control circuit DRAM control circuit

1994-09-09

1996-11-12

Rudolph, Rebecca L.

Boots, shoes, and leggings

364DIG1, 364260, 364244, 395432, G11C 700

Patent

active

055748848

ABSTRACT:
A DRAM control circuit according to the present invention, comprising a DRAM, a DRAM controller adapted for receiving an address, write data, and a data rewrite command from a host controller and designating a row address and a column address to the DRAM, and a column address strobe signal control circuit, causes pseudo column address strobe signal DCASq-N to have "L" level to read the contents of the address when column address strobe signal DCAS-N and read signal RD-N have "L" level, causes pseudo column address strobe signal DCASq-N to have "H" level to set an input/output terminal I/O to high impedance when the read signal RD-N has "H" level, further causes pseudo write signal WR-q to have "L" level to output write data to a data bus when the input/output terminal I/O remains at the high impedance, and rewrites the contents of the address to the write data when the pseudo column address strobe signal DCASq-N is caused to have "L" level.

REFERENCES:
patent: 5469558 (1995-11-01), Lieberman et al.
patent: 5479111 (1995-12-01), Matsuura
patent: 5488691 (1996-01-01), Fuoco et al.
patent: 5491828 (1996-02-01), Intrater et al.
"HB56G51232 Series, Hitachi IC Memory Data Book 3", Semiconductor Division, Hitachi Co., Ltd., 14th edition, 1992, pp. 922-924.

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