Redundancy circuit for repairing defective bits in semiconductor

Details Redundancy circuit for repairing defective bits in semiconductor Redundancy circuit for repairing defective bits in semiconductor

1994-11-10

1996-11-12

Beausoliel, Jr., Robert W.

Excavating

371 102, 365200, G06F 1100

Patent

active

055747299

ABSTRACT:
A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4849938 (1989-07-01), Furutani et al.
patent: 5083294 (1992-01-01), Okajima
patent: 5134585 (1992-07-01), Murakami et al.
patent: 5227999 (1993-07-01), Ihara et al.
"A 7NS 1MB BiCMOS ECL SRAM with Program-Free Redundancy" Ohba et al, CH2885-Feb. 1990 IEEE pp. 41-42.

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