Speed enhancement technique for CMOS circuits

Details Speed enhancement technique for CMOS circuits Speed enhancement technique for CMOS circuits

1990-04-24

1991-01-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307542, 307550, 307548, 307451, 307594, H03K 19003, H03K 19017, H03K 1704, H03K 17687

Patent

active

049856430

ABSTRACT:
A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from subsequent logic stages. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting part of the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

REFERENCES:
patent: 3603810 (1971-09-01), Clayson
patent: 3700916 (1972-10-01), Vittoz
patent: 4476401 (1984-10-01), Lin
patent: 4490627 (1984-12-01), Moench et al.
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4700089 (1987-10-01), Fujii et al.
patent: 4728820 (1988-03-01), Lee
patent: 4806786 (1989-02-01), Valentine
Towler, Fred, et al., "A 128k 6.5ns Access/5ns Cycle CMOS ECL Static RAM"; Digest of Technical Papers; 1989 IEEE International Solid-State Circuits Conference; pp. 30-33.
Krambeck et al., "High Speed Compact Circuits Using CMOS", IEEE Journal of Solid State Circuits, vol. SC-17, No. 3, pp. 614-619, Jun. 1982.
Adams, R. Dean, et al., "FAM 16.4: An 11ns 8Kx18 CMOS Static RAM"; Digest of Technical Papers, 1988 IEEE International Solid-State Circuits Conference; pp. 242-243, 386.
Shoji, M., "FET Scaling in Domino CMOS Gates," IEEE Journal of Solid-State Circuits (Oct. 1985), SC-20(5):1067-1071.
Oklobdzija, V. G., et al., "Design-Performance Trade-Offs in CMOS Domino Logic," IEEE 1985 Custom Integrated Circuits Conference, CH2157-6/85/0000-0334, pp. 334-337.
Pretorius, J. A., et al., "Optimization of Domino CMOS Logic and Its Applications to Standard Cells," IEEE 1984 Custom Integrated Circuits Conference, CH1987-7/84/000-0150, pp. 150-153.
Pretorius, J. A., et al., "Analysis and Design Optimization of Domino CMOS Logic with Application to Standard Cells," IEEE Journal of Solid-State Circuits (Apr. 1985) SC-20(2):523-530.
Hofmann, M., et al., "A Domino CMOS Logic Synthesis System", 1985 International Symposium on Circuits and Systems (Jun. 1985) 2:4111.varies.414.
Oklobdzija, V. G., et al., "Design-Performance Trade-Offs in CMOS-Domino Logic," IEEE Journal of Solid-State Circuits (Apr. 1986) SC-21(2):304-306.
Pretorius, J. A., et al., "Charge Redistribution and Noise Margins in Domino CMOS Logic," IEEE Transactions on Circuits and Systems (Aug. 1986) CAS-33(8):786-793.
Pretorius, J. A., et al., "Testability Enhancement of Domino CMOS Logic," Electronics Letters (Apr. 1985) 21(8):336-337.
Oklobdzija, V. G., et al., "On Testability of CMOS-Domino Logic," IEEE 14th Int. Conf. on Fault-Tolerant Computing (1984) 0731-3071/84/0000/0050, pp. 50-55.
Zhang, C., "An Improvement for Domino CMOS Logic," Comput. & Elect. Engng. (1987) 13(1):53-59.
Pretorius, J. A., et al., "Latched Domino CMOS Logic," IEEE Journal of Solid-State Circuits (Aug. 1986) SC-21(4):514-522.
Pretorius, J. A., et al., "Latched Domino CMOS Logic," Electronics Letters (Mar. 1985) 21(7):263-264.
Murphy, B. T., et al., "Twin Tubs, Domino Logic, CAD Speed Up 32-bit Processor," Electronics (Oct. 1981), pp. 106-111.
Heller, L. G., et al., "Cascade Voltage Switch Logic: A Different CMOS Logic Family," 1984 IEEE International Solid-State Circuits Conference (Feb. 1984) 0193-6530/84/0000/0016, pp. 16-17.

Affiliated with

Also associated with

Rating

Speed enhancement technique for CMOS circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Speed enhancement technique for CMOS circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Speed enhancement technique for CMOS circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-56851