Method for fabricating a stacked capacitor in a DRAM cell

Details Method for fabricating a stacked capacitor in a DRAM cell Method for fabricating a stacked capacitor in a DRAM cell

1996-02-02

1996-10-08

Niebling, John

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 218242

Patent

active

055630880

ABSTRACT:
The present invention provides a method of manufacturing a capacitor for a DRAM which is characterized in that after forming a first conductive layer, an oxidation barrier layer (e.g., silicon nitride) and a polysilicon layer over associated field effect transistors, an opening is formed in the polysilicon layer over the contact node (e.g., source region) of the DRAM FET. The polysilicon layer is the oxidized thereby reducing the area of the opening below that of conventional photolithography limits. The oxidation barrier layer and the first conductive layer are anisotropically etched using the oxidized polysilicon layer as a mask. The polysilicon layer and oxidation barrier layer are then removed. Next, the first conductive layer is patterned into a bottom electrode. A dielectric layer and a top electrode are formed over the bottom electrode to complete the capacitor and DRAM of the present invention.

REFERENCES:
patent: 5104821 (1992-04-01), Choi et al.
patent: 5508223 (1996-04-01), Tseng
patent: 5521112 (1996-05-01), Tseng

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