Dynamic precharge circuitry

Details Dynamic precharge circuitry Dynamic precharge circuitry

Filed on

1976-09-01

Date issued

1978-05-23

Examiner

Pitts, Harold I.

Patent Class

Communications: electrical

SubClass

Digital comparator systems

Other Related Categories

365203, G11C 700

Type

Patent

Status

active

Patent number

040913600

Description

ABSTRACT:
In MOS circuitry, such as a dynamic MOS random access memory, precharge circuitry, consisting of six p-channel MOS transistors and a seventh p-channel MOS transistor connected as a capacitor, facilitates a two step charging process that initially lowers the potential of a first circuit node from a high potential to a value approximately one threshold voltage above an available low level power supply potential and then further lowers the potential of the circuit node to a value below that of the available low level power supply potential. A single voltage pulse and the complement thereof are the only input signals required. Normal threshold voltage losses of MOS transistors can thus be effectively eliminated and noise margins thereby improved.

REFERENCES:
patent: 3720925 (1973-03-01), Ross
patent: 3816725 (1974-06-01), Greer
patent: 3914620 (1975-10-01), Millhollan

Affiliated with

Also associated with

Rating

Dynamic precharge circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic precharge circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic precharge circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-566808