Dual clocking time delay generation circuit

Details Dual clocking time delay generation circuit Dual clocking time delay generation circuit

1981-05-26

1983-04-05

Heyman, John S.

Boots, shoes, and leggings

328 62, 328 72, 364900, H03L 700, H03K 515

Patent

active

043792650

ABSTRACT:
A control circuit for generating first and second clocking pulses as outputs wherein there is a controlled time delay between the first and the second clocking pulses. The delay time, d.sub.i, between the first and second clocking pulses can be controlled as to the duration of the delay and also can be placed on an automatic sequence basis wherein the time delay d.sub.i period will automatically readjust to a series of smaller time delay periods.

REFERENCES:
patent: 3983498 (1976-09-01), Malek
patent: 4131856 (1978-12-01), Chapman
patent: 4241418 (1980-12-01), Stanley
patent: 4313206 (1982-01-01), Woodward
patent: 4359689 (1982-11-01), Guenthner

Affiliated with

Also associated with

Rating

Dual clocking time delay generation circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual clocking time delay generation circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual clocking time delay generation circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-566407