Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Patent
1995-09-28
1996-11-12
Grimm, Siegfried H.
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
331 14, 331 17, 331 20, 331 25, 348540, 348542, H03L 7113
Patent
active
055744060
DESCRIPTION:
BRIEF SUMMARY
The invention relates to an arrangement for generating a clock signal.
Digital video signal processing systems with features such as on-screen display of text and picture-in-picture for both television receiver and video tape recorder signal sources may require a clock signal that is phase locked to a horizontal synchronization signal, referred to as line-locked clock. It may be advantageous to form a phase-locked loop (PLL) system for line-locked clock generation for use as a building block in large scale CMOS video signal processing integrated circuits. In such PLL, it may be desirable to have, for example, a clock frequency that ranges from 25 MHz to 40 MHz with a jitter that is less than 2nS. For such PLL it may be desirable to utilize only one pin for offchip components. It may also be desirable to use the PLL system with each of the NTSC, PAL and SECAM systems.
It may also be advantageous to operate the PLL with input sync signal encountered in low-cost consumer video tape recorders without time-base correction where the horizontal sync can periodically make large phase changes such that the clock signal tracks such sync signal. It may be further desirable to rapidly reduce phase and frequency errors and minimize overshoot and jitter as the PLL settles into phase lock. In addition, it may be desirable to have the PLL discriminate between true output clock phase/frequency errors and those arising from contamination of the input horizontal sync signal with noise bursts or occasional missing pulses.
A PLL system, embodying an inventive feature, utilizes both digital and analog control of an R-C Voltage-Controlled Oscillator to acquire and maintain phase lock of an output clock with respect to an input horizontal sync signal. Depending on the magnitude and consistency of the output clock phase and frequency error, the system automatically selects one of, for example, five control modes of operation of varying sensitivity. The control modes of operation are such that large errors result in large, coarse corrective actions, and small errors result in small, or fine corrective actions. A frequency detector measures a frequency error between an output of an oscillator and a horizontal sync signal for operating the PLL in a frequency error control mode of operation when the frequency error exceeds a first value. When the frequency error does not exceed the first value, the PLL operates in a phase error control mode of operation.
In accordance with another inventive feature, in the frequency error control mode of operation, the measurement of the frequency error occurs in alternate horizontal line periods. Whereas, variation of the oscillator frequency for correcting the frequency error occurs in other alternate horizontal line periods. Advantageously, the measurement and correction of the frequency error occur in non-overlapping horizontal line periods. The result is a more stable and better controllable feedback loop. On the other hand, in a phase error correction mode of operation, correction of the phase error and measurement of the phase error occur simultaneously in the same horizontal line period.
An apparatus, embodying an inventive feature, for generating an oscillatory signal includes a source of a synchronizing signal at a frequency that is related to a horizontal scanning frequency. A controllable oscillator for generating the oscillatory signal is provided. A detector responsive to the oscillatory and synchronizing signals is used for measuring a cycle related error therebetween and for generating a signal that is indicative of the error. The error indicative signal is coupled to the oscillator for varying a cycle of the oscillatory signal when the error exceeds a first value. The variation of the cycle of the oscillatory signal and the measurement of the error occur, alternately, in non-overlapping periods.
FIG. 1 illustrates a block diagram of a phase-lock-loop (PLL), embodying an aspect of the invention;
FIGS. 2A, 2B and 2C illustrate a detailed schematic diagram of a programmable switched R-C
REFERENCES:
patent: 4484152 (1984-11-01), Lee
patent: 4498059 (1985-02-01), Edwards et al.
patent: 4514705 (1985-04-01), Harzer
patent: 4516118 (1985-05-01), Wahlquist
patent: 4531102 (1985-07-01), Whitlock et al.
patent: 4580107 (1986-04-01), Caldwell et al.
patent: 4594564 (1986-06-01), Yarborough, Jr.
patent: 4616259 (1986-10-01), Moran et al.
patent: 4654604 (1987-03-01), Smith et al.
patent: 4745372 (1988-05-01), Miwa
patent: 4797634 (1989-01-01), Filliman
patent: 4812783 (1989-03-01), Honjo et al.
patent: 4827225 (1989-05-01), Lee
patent: 4837781 (1989-06-01), Hickling
patent: 4843332 (1989-06-01), Cok et al.
patent: 4878231 (1989-10-01), Cok
patent: 4881048 (1989-11-01), Auneau et al.
patent: 4890071 (1989-12-01), Curtis
patent: 4918405 (1990-04-01), Herleikson
patent: 4920320 (1990-04-01), Matthews
patent: 4920322 (1990-04-01), Ruijs
patent: 4935706 (1990-06-01), Schenberg
patent: 4974081 (1990-11-01), Yokogawa
patent: 5159292 (1992-10-01), Canfield et al.
patent: 5162910 (1992-11-01), Willis
patent: 5172076 (1992-12-01), Brown
patent: 5239274 (1993-08-01), Chi
patent: 5298870 (1994-03-01), Cytera et al.
IBM Technical Disclosure Bulletin, vol. 23, no. 1, 1 Jun. 1980, New York US, pp. 81-82; M. Carnes et al. "Cycle Schronised Phase-Locked Loop".
IBM Technical Disclosure Bulletin, vol. 26, no. 1., 1 Jun. 1983, New York US, pp. 6-8, H. Keller et al. "Phase Locked Loop Circuitry Comprising a Watchdog Circuit for Instability Suppression".
Campbell, III Edward R.
Rodda William E.
Sauer Donald J.
Grimm Siegfried H.
Henig Sammy S.
Laks Joseph J.
RCA Thomson Licensing Corporation
Tripoli Joseph S.
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